Article ID: 000075945 Content Type: Product Information & Documentation Last Reviewed: 12/31/2013

How do I enable the Stratix® IV GX device to pass the PCI Express Electrical Gold test requirements on the v2.0 Compliance Base Board (CBB)?

Environment

  • Stratix® IV GX FPGA
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The PCI Express Electrical Gold Test requires the v2.0 CBB to be connected to the Device Under Test (DUT).   The CBB sends out a 100MHz signal for 1ms to indicate the Link Training and Status State Machine (LTSSM) of the downstream device Under Test (DUT) to transition to several polling compliance states. Under these states, the DUT sends out data at Gen1, Gen2 (with -3.5db deemphasis) and Gen2 (with -6db deemphasis) rates which can be observed in the scope to confirm the electrical signal compliance. The CBB is DC coupled to the downstream receiver.

    When Stratix® IV GX device is used as DUT, because of being DC coupled to CBB with different common mode level, the Stratix IV GX receiver does not receive the required common mode voltage (0.85v) to detect the signal. Therefore the logic in the FPGA fabric that implements LTSSM cannot transition to the multiple polling compliance states to complete the test.

    Resolution When testing with the CBB,  force the LTSSM implemented in the FPGA fabric to transfer to different polling compliance states using an external push button or user logic. If you are using the Stratix IV GX PCIExpress hard IP block, assert the  testin[5] port of the PCIExpress Compiler generated wrapper file in your design.  Asserting this port forces the LTSSM within the hard IP block to transition to these states. The testin[5] port should be asserted for a minimum of 16ns and less than 24ms.

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