Article ID: 000075941 Content Type: Troubleshooting Last Reviewed: 09/30/2011

IP Compiler for PCI Express Stratix IV GX Reset Controller Does Not Enter Recovery Immediately if Reference Clock Constraints are Not Met

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    The reset controller logic for the IP Compiler for PCI Express hard IP implementation with internal reset modules on Stratix IV GX devices does not monitor the pll_locked state after the busy_altgxb_reconfig signal is deasserted. As a result, you may observe link instability before the IP Compiler for PCI Express goes into link recovery following loss of PLL lock.

    This issue affects all IP Compiler for PCI Express hard IP implementations with internal reset modules on Stratix IV GX devices.

    Resolution

    To avoid this issue, ensure that your IP Compiler for PCI Express transceiver reference clock meets the following requirements:

    • The reference clock must be a free running clock that is valid after the device powers up.
    • The reference clock must remain stable during normal operation, soft reset, hot reset, powerdown, Link Down state, and other expected situations.

    This issue will not be fixed in a future version of the IP Compiler for PCI Express. Correct operation requires that the design follow the reference clock constraints described in the Workaround section.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs

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