Article ID: 000075935 Content Type: Troubleshooting Last Reviewed: 06/18/2013

Can the frequency of the PLL output clock change after manual clock switchover?



Yes, depending on the secondary input reference clock frequency that user is switching to, the PLL output clock frequencies can change. This is because the PLL counter settings will remain constant during the manual clock switchover and therefore the new output clock frequency will be based on the new input reference clock and the PLL counter settings. For example: 


Settings from the altpll megafunction 


Inclk0 = 20 MHz

Inclk1 = 18 MHz

Output = 100 MHz


N counter = 1

M counter = 30

Post scale counter = 6

VCO = 600 MHz


In this case, when the input clock is manually switched from inclk0 to inclk1, the new output frequency is now 90 MHz rather than 100MHz based on the above settings.


Note that changing the input frequency may cause the PLL to lose lock, but as long as the input clock remains within the minimum and maximum lock range frequency, the PLL will be able to achieve lock.


Refer to the respective device handbook for more details and guidelines for using manual clock switchover.

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Cyclone® III FPGAs