Due to a problem in the auto generated Synopsys Design Constraint (.sdc) files for the Triple Speed Ethernet IP you may see "Ignored filter" warnings such as the example below during timing analysis when your design hierarchy contains backslashes:
Ignored filter at altera_eth_tse_pcs_pma_lvds.sdc(158): "<path to tse register>" could not be matched with a register
Your design may also experience timing violations as a result of these ignored constraints.
This problem exists for the Triple Speed Ethernet IP targeting the Arria® V, Arria 10 , Cyclone® V and Stratix® V device families generated in the Quartus® Prime Software versions 16.0.2 and earlier.
To work around this problem search for the following strings within the auto generated sdc files:
set inst_list [query_collection -list -all $inst ]
foreach each_inst $inst_list{
And replace both lines with the following:
foreach_in_collection each_inst_tmp $inst {
set each_inst_name [get_node_info -name $each_inst_tmp ]
regsub {\\} $each_inst_tmp {*} each_inst
Note that these sdc files will be overwritten each time the IP is regenerated so make copies and ensure that the edits are applied to the most recent sdc file.
This problem is scheduled to be resolved in a future release of the Quartus Prime Software.