Article ID: 000075916 Content Type: Troubleshooting Last Reviewed: 09/11/2012

When I simulate the PCI Express (PIPE) x8 configuration in Stratix IV GX device, why is the coreclkout [1] port always at logic low?

Environment

  • Stratix® IV GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When you instantiate the Stratix® IV GX transceiver in PCI Express (PIPE) x8 configuration, the ALTGX MegaWizard® Plug-in Manager provides two bits for the coreclkout output port, one for each transceiver block.

 

Altera has identified that during functional simulation of the above configuration, the coreclkout[1] is always stuck at logic zero. The expected behavior is to have transitions on both coreclkout[0] and coreclkout[1].

 

Workaround: Altera recommends that you use only the coreclkout[0] port to clock the user logic in your design.

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