Description Due to a problem in the Quartus® II software version 12.1, you may see this internal error if you instantiate an ALTCLKCTRL block and connect
inclk1xports to clock pins that are not on the same side of the device. This restriction applies to designs targeting Stratix® V and Arria® V devices.
To avoid this problem, connect ALTCLKCTRL input ports to clock pins on the same side of the device.
Future versions of the Quartus II software are scheduled to generate an error message for this illegal connection.