Article ID: 000075896 Content Type: Error Messages Last Reviewed: 02/04/2013

Internal Error: Sub-system: ASMCC, File: /quartus/comp/asmcc/asmcc_bitfield.cpp, Line: 989

Environment

  • Quartus® II Subscription Edition
  • Clock
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® II software version 12.1, you may see this internal error if you instantiate an ALTCLKCTRL block and connect inclk0x and inclk1x ports to clock pins that are not on the same side of the device. This restriction applies to designs targeting Stratix® V and Arria® V devices.
    Resolution

    To avoid this problem, connect ALTCLKCTRL input ports to clock pins on the same side of the device.

    Future versions of the Quartus II software are scheduled to generate an error message for this illegal connection.

    Related Products

    This article applies to 9 products

    Arria® V ST SoC FPGA
    Stratix® V E FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Arria® V GX FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Stratix® V GS FPGA
    Arria® V GT FPGA

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