Article ID: 000075856 Content Type: Troubleshooting Last Reviewed: 05/25/2016

In which clock domain of the Arria 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core are the following signals, led_link, led_char_err, led_disp_err, and led_an.

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The clock domain of led_link, led_char_err, led_disp_err, and led_an signals for the Arria® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core is an internal clock domain. Because you cannot use the internal clock in the FPGA fabric, these led_* signals need to be treated as asynchronous signals.

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Intel® Programmable Devices