When using the Altera® PLL Reconfig megafunction for Dynamic Phase Shift, reconfiguration will not occur if the Start register is written immediately after the Dynamic Phase Shift register is written. This will be evident because the waitrequest signal on the Avalon-MM interface will not be asserted.
This is due to a bug in the megafunction which will be fixed in a future version of the Quartus® II software.
To ensure reconfiguration takes place, there must be at least one mgmt_clk cycle between the first write to the Dynamic_Phase_Shift register and the write to the start register.
For more details on the operation of the Altera PLL reconfig MegaFunction, refer to AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions (PDF).