Description
Due to a problem in the timing model in Quartus® Prime version 15.1, you may see timing violations in the MAX®10 On-Chip Flash on the following register:
*altera_onchip_flash_block:altera_onchip_flash_block|drdout[0]
Note that this register is both the source and destination for the hold violation.
Resolution
This violation is false and can be ignored. It is scheduled to be resolved in a future release of the Quartus Prime software.
