Description
Due to the cross-clocking nature of the DCFIFO IP, the latency of the Status Flags could be 1 greater than that specified in the SCFIFO and DCFIFO IP Cores User Guide (PDF).
Environment
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Related Products
This article applies to 31 products
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Intel® MAX® 10 FPGAs
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Stratix® V GS FPGA
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Stratix® IV GX FPGA
Arria® II GX FPGA
Intel® Arria® 10 GX FPGA
Arria® II GZ FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Intel® Arria® 10 SX SoC FPGA
MAX® V CPLDs
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA