Description
The PLL reconfiguration feature is useful in applications that might operate at different frequencies and/or switch between multiple I/O standards and proctocols.
The PLL feature is also useful in prototyping environments where a designer could easily sweep PLL output frequencies and adjust clock delay. For instance, a system generating test patterns might be required to generate and transmit patterns at 50 MHz or 100 MHz, depending on the unit under test. Real-time reconfiguration of PLL components allows system designers to switch between two such output frequencies within 20 ms. Designers could also use this feature to adjust clock-to-out (tco) delays in real time by changing output clock delay. This approach eliminates the need both to regenerate a programming file with the new PLL settings and to reconfigure the entire device.