This problem is fixed in the Quartus II software version 2.2.
The ROM will function correctly in simulation because the simulation netlist is not affected by his problem. The Quartus II fitter can pack ROM and RAM into ESB memory blocks to optimize device resources, and in most cases all signals are wired corrects for both memory blocks. However, in the Quartus II software version 2.1 SP1 and lower, when a ROM is packed with another ROM or a single-port RAM, the programming file does not correctly wire up the address lines for the ROM. For this reason, the APEX II device will not function correctly on your board. For example, you may read zeros from all ROM addresses when the APEX II is programmed or configured.
As a workaround, you may do one of the following:
- Implement the ROM in logic elements (LEs) instead of embedded system memory (ESB blocks) - you may need to turn off RAM inference in your synthesis tool.
- Make individual ESB location assignments to each of your ROMs and single-port RAMs to ensure that they are not placed in the same ESB by the Quartus II fitter.
- Convert all ROMs to single-port RAMs with the write enable set to ground (GND).