Article ID: 000075751 Content Type: Product Information & Documentation Last Reviewed: 09/01/2014

How do I view the external memory signals in my HPS SDRAM simulation?

Environment

  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The HPS simulation model does not use external memory pins to connect to the DDR2, DDR3 or LPDDR2  memory model. The actual memory model is created internally in the following hierarchy:

    hps_0/fpga_interfaces/f2sdram/hps_sdram_inst/mem/

    You will need to view the external signals at this level.

    Related Products

    This article applies to 5 products

    Cyclone® V SE SoC FPGA
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    Arria® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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