Article ID: 000075735 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Why do I get the following error message when using the PCI Express HardIP "Error: PLL "<variation name>_example_chaining_pipen1b:core|<variation name>_plus:ep_plus|<variation name>:epmap|<<variation name>_serdes:serdes|<variation name>_serdes_alt_c3gxb_a


  • PCI Express

    The below error occurs when you use the PCI Express® HardIP and if you have installed Quartus® II with only a limited set of devices. For example, only Cyclone® IV GX device support has been installed.

    To workaround this error, you can simply re-install Quartus II ensuring that all device famlies are installed, and then regenerate the PCI Express IP.

    This problem will be fixed in a future version of the Quartus II software.


     Error: PLL "&lt;variation name&gt;_example_chaining_pipen1b:core|&lt;variation name&gt;_plus:ep_plus|&lt;variation name&gt;:epmap|<&lt;variation name&gt;_serdes:serdes|&lt;variation name&gt;_serdes_alt_c3gxb_aac8:&lt;variation name&gt;_serdes_alt_c3gxb_aac8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK[0] connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0

    Related Products

    This article applies to 5 products

    Arria® II GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Arria® II GZ FPGA
    Cyclone® IV GX FPGA