The PLL simulation is configured 64steps per cycleand limited to stepping by 1 ps granularity. For some frequency settings, the pll steps have decimal points when divided to 64steps and the PLL step duration will be rounded. Since the altmemphy IP continuously increments the phase, it would not take long for the simulation to eventually accumulate enough error to be fully 180 degrees out of cycle.
To workaround this issue, calculate PLL reference clock value that nearest to the target value for simulation.
Example:
For 24.576MHz (40.690ns), the PLL is configured 64steps per cycle. Hence, it takes 635.78ps per step. The PLL simulation is limited to stepping by 1 ps granularity, so it uses 636 ps per step. Since the altmemphy IP continuously increments the phase, it would not take long for the simulation to eventually accumulate enough error to be fully 180 degrees out of cycle.
To avoid such errors in this frequency range, determine a value that is multiple of 64 which is 24.606MHz (this value is nearer to 24.567MHz).
In actual application, we still can remain the actual reference frequency.