Article ID: 000075716 Content Type: Troubleshooting Last Reviewed: 09/17/2018

Why is the timestamp value of the Intel® Stratix® 10 Hard IP for PCI Express* IP Link Inspector overestimated?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem in the Intel® Stratix® 10 Hard IP for PCI Express* Link Inspector, you may observe that the timestamp value is larger than the actual time.

    For example, when using the Intel® Stratix® 10 Hard IP for PCI Express* coreclkout at 125MHz, the timestamp value will show approximately 20% over the estimated value (12ms compared to the actual 10ms).

    This is due to a discrepancy between the user defined coreclkout at 125MHz or 250MHz, and the 100MHz clock always used by Link Inspector.

    Resolution

    To work around this problem, apply a multiplication factor on the timestamp value as shown below.

    When using a 125MHz coreclkout, multiply the timestamp value with multiplication factor of 0.8 (100MHz / 125MHz).

    When using a 250MHz coreclkout, multiply the timestamp value with multiplication factor of 0.4  (100MHz / 250MHz).

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

     

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