Article ID: 000075696 Content Type: Error Messages Last Reviewed: 09/11/2012

Warning: PLL cross checking found inconsistent PLL clock settings: Warning: Node: <PLL output clock name> was found missing 1 generated clock that corresponds to a base clock with a period of: lgt:PLL input clock periodrlt:

Environment

  • Stratix® III FPGAs
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Description

You might get this warning message if the PLL output clock(s) is not constrained properly in the SDC file.

Constrain all PLL output clocks in one of the following ways:

1. Use 'derive_pll_clocks' to automatically constrain the PLL output clocks, or

2. Use 'create_generated_clock' to constrain the PLL output clocks individually.

Refer to High-Performance FPGA PLL Analysis with TimeQuest (PDF) for further details about PLL analysis with TimeQuest.

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