You might get this warning message if the PLL output clock(s) is not constrained properly in the SDC file.
Constrain all PLL output clocks in one of the following ways:
1. Use 'derive_pll_clocks' to automatically constrain the PLL output clocks, or
2. Use 'create_generated_clock' to constrain the PLL output clocks individually.
Refer to High-Performance FPGA PLL Analysis with TimeQuest (PDF) for further details about PLL analysis with TimeQuest.