Article ID: 000075695 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is the rx_phase_comp_fifo_error output port of the Stratix IV GX transceiver always at an undefined state during functional simulation?

Environment

  • Stratix® IV GX FPGA
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Description

Altera has identified that during functional simulation of Stratix® IV GX transceiver instance, the rx_phase_comp_fifo_error output port is always at an undefined state . This is a known issue. Altera recommends you not to use this port for simulation of Quartus® II software version 8.0 designs.

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