Article ID: 000075689 Content Type: Troubleshooting Last Reviewed: 07/16/2021

Why does the Intel® FPGA P-Tile Avalon Streaming IP for PCI Express* Design Example export reconfiguration interfaces to top level pins, ports?

Environment

  • Intel® Agilex™ I-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    Due to a problem with the Intel® FPGA P-Tile Avalon Streaming IP for PCI Express* Design Example, reconfiguration interfaces are incorrectly exported to top level pins/ports?

    This can cause design instability depending on the signals connected to these pins on the actual PCB.

    The following signals are incorrectly exported to the top level.

    dummy_user_avmm_rst_reset
    p0_config_tl_dl_timer_update
    xcvr_reconfig_read
    xcvr_reconfig_readdatavalid
    xcvr_reconfig_waitrequest
    xcvr_reconfig_write
    p0_config_tl_tl_cfg_add
    p0_config_tl_tl_cfg_ctl
    p0_config_tl_tl_cfg_func
    p0_tx_cred_tx_cdts_type
    p0_tx_cred_tx_data_cdts_consumed
    xcvr_reconfig_address
    xcvr_reconfig_writedata
    xcvr_reconfig_readdata

    Resolution

    To work aorund this problem modify the top level rtl to stop these signals being exported, or use virtual pin assignment to achieve the same.

    This problem is schedule to be fixed in a future release of the Intel® Quartus® Prime software.

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