Due to a problem with the Intel® FPGA P-Tile Avalon Streaming IP for PCI Express* Design Example, reconfiguration interfaces are incorrectly exported to top level pins/ports?
This can cause design instability depending on the signals connected to these pins on the actual PCB.
The following signals are incorrectly exported to the top level.
To work aorund this problem modify the top level rtl to stop these signals being exported, or use virtual pin assignment to achieve the same.
This problem is schedule to be fixed in a future release of the Intel® Quartus® Prime software.