Due to a problem with the Intel® FPGA P-Tile Avalon Streaming IP for PCI Express* Design Example, reconfiguration interfaces are incorrectly exported to top-level pins/ports?
This can cause design instability depending on the signals connected to these pins on the actual PCB.
The following signals are incorrectly exported to the top level.
dummy_user_avmm_rst_reset
p0_config_tl_dl_timer_update
xcvr_reconfig_read
xcvr_reconfig_readdatavalid
xcvr_reconfig_waitrequest
xcvr_reconfig_write
p0_config_tl_tl_cfg_add
p0_config_tl_tl_cfg_ctl
p0_config_tl_tl_cfg_func
p0_tx_cred_tx_cdts_type
p0_tx_cred_tx_data_cdts_consumed
xcvr_reconfig_address
xcvr_reconfig_writedata
xcvr_reconfig_readdata
To work around this problem modify the top-level RTL to stop these signals from being exported, or use virtual pin assignment to achieve the same.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.