Article ID: 000075685 Content Type: Troubleshooting Last Reviewed: 03/10/2021

Why is the rx_st_valid signal not asserted in the Intel® L- and H-tile Avalon® Streaming for PCI Express* IP when receiving an Unsupported Request (UR) completion?

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Stratix® 10 NX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    Due to a problem with the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, you may encounter the above problem when receiving an Unsupported Request (UR) completion on physical functions(PF) 2 and 3.

    Resolution

    There is no workaround for this problem.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro software.

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