Article ID: 000075681 Content Type: Troubleshooting Last Reviewed: 04/28/2017

Why are the Low Latency 40G/100G Ethernet IP pause timers off by a factor of two?

Environment

  • Stratix® V GS FPGA
  • Stratix® V GX FPGA
  • Stratix® V GT FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • Low Latency 40G 100G Ethernet
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    Critical Issue

    Description

    Due to a problem with the Intel® Low Latency 40G Ethernet IP core, you will see the pause counters increment twice as fast as expected.  You will see this behavior for both Standard Flow Control and Priority Flow Control modes.

    Resolution

    This problem has been fixed in the Intel Quartus® Prime version 16.0 software.

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