Why do I get a simulation error when simulating the P-Tile Avalon® Streaming SRIOV IP for PCI Express* Design Example for Agilex™ 7 FPGA devices using Modelsim* FPGA Edition?

Due to a problem in the FPGA P-Tile Avalon® Streaming IP for PCI Express*, an error will be observed when trying to simulate the Agilex™ 7 FPGA 3.0x4 SR-IOV design example using ModelSim*  FPGA Edition.

The following error message will be seen: 

# **Error: (vsim-3033) Instantiation of 'ctp_tile_encrypted' failed. The design unit was not found.

#   Time: 0 ps  Iteration: 0  Instance:/pcie_ed_tb/pcie_ed_inst/dut/dut/inst/inst/maib_and_tile/z1565a File: $MODEL_TECH/../altera/verilog/src/ctp_hssi_atoms.sv Line: 39100

There is no workaround available. This problem is not scheduled to be fixed in any future release of the Quartus® Prime Software.

Use a supported simulation tool like the Mentor* Graphics ModelSim* SE or Synopsys VCS*.