Article ID: 000075656 Content Type: Troubleshooting Last Reviewed: 03/12/2021

Why does the Intel® L-tile and H-tile Avalon® Streaming and Avalon® Memory Mapped IP for PCI Express* observe correctable errors/link down train when operating in Gen3 Root Port mode?

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 NX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    When using the Intel® L-tile and H-tile Avalon® Streaming and Avalon® Memory Mapped IP for PCI Express* in Gen3 Root Port mode, correctable errors or link down training may be observed due to sub-optimal preset bit settings for PCIe* Upstream Port (USP)/Downstream Port (DSP) Gen3 Root Port IP on both H tile and L tile.

    Resolution

    No work around to this problem exists in Intel® Quartus® Prime software versions 20.2 and earlier.

    This problem has been fixed in Intel® Quartus® Prime software versions 20.3 and later.

    If upgrading from an earlier version of the software, the IP should be generated from clean to avoid inporting the earlier sub-optimal settings.

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