Article ID: 000075637 Content Type: Troubleshooting Last Reviewed: 02/15/2018

Why does my PCI Express* Hard IP drop some receive TLPs?

Environment

    Intel® Quartus® Prime Pro Edition
    PCI Express
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Description

You may see this problem if the host software sets the Max Payload Size in the Device Control register higher than the Maximum Payload Size Supported on the Device Capabilities register. Maximum Payload Size Supported is a parameter which is configured in the IP editor. Host software must probe every device to determine its MPS capability and determine the proper system wide MPS setting per the PCIe* spec.

Resolution

To work around this problem ensure host software sets the Max Payload Size in the Device Control register to be no greater than the value of Maximum Payload Size Supported in the Device Capabilities register.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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