Article ID: 000075629 Content Type: Troubleshooting Last Reviewed: 06/15/2021

Why are the Tx and Rx PTP Ready signal of the E-Tile Hard IP for Ethernet Intel® FPGA IP not asserted after Tx or Rx reset in PTP Advanced Mode ?

Environment

  • Intel® Agilex™ FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition version 21.1 software,  you may observe the o_tx_ptp_ready and o_rx_ptp_ready of the E-Tile Hard IP for Ethernet Intel® FPGA IP do not assert after toggling either of the i_sl_tx_rst_n or i_sl_rx_rst_n reset port in PTP Advanced Mode.

    The PTP Basic Mode is not impacted by this problem.

     

    Resolution

    To work around this problem in PTP Advanced Mode, you must toggle both of the i_sl_tx_rst_n and i_sl_rx_rst_n reset ports in order for o_tx_ptp_ready and o_rx_ptp_ready to be asserted.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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