Article ID: 000075625 Content Type: Troubleshooting Last Reviewed: 03/15/2019

Why does the FIR II Intel FPGA IP core's decimation mode cannot pack the pre-adder and input register into the DSP block?

Environment

    Intel® Quartus® Prime Pro Edition
    FIR II Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem with the Intel® Quartus® Prime software, the pre-adder and input register of decimating FIR II Intel FPGA IP core cannot pack into the DSP block if the coefficient and input data widths are of 19 bits and 18 bits. It may also have significant impact on the design timing performance. 

Resolution

Use coefficients width of 18 or 20 bits. This problem will be fixed in a future version of the Quartus Prime software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.