To use the Hard IP for PCI Express® test bus in conjunction with SignalTap™ II, a register map, or general purpose IOs to observe the PIPE interface signals on Arria® V GZ and Stratix® V devices. Follow the instructions below:
The test bus consists of test_in bus and test_out bus. The test bus is designed for debugging purposes only and should not be used in production designs.
The test_in bus determines which Hard IP PIPE interface signals to route to the test_out bus for observation. The upper 32 bits of the test_in bus in the file altpcie_sv_hip_ast_hwtcl.v is used to select two of eight PCIe lanes. The PIPE signals for these two lanes are routed to the 320 bit test_out bus (also refered to as testout in the same file).
1. Determine the value for the upper 32 bits of the test_in bus
Only the upper 32 bits of the test_in bus are used to select the PIPE interface signals for two specific PCIe lanes at a time. Table 1 shows the test_in[63:32] value to select the lanes.
test_in[63:32] | PIPE Interface Signal Lane Selection |
32'h0 | lane0 and lane1 |
32'h1 | lane2 and lane3 |
32'h2 | lane4 and lane5 |
32'h3 | lane6 and lane7 |
Table 1. Test_in[63:32] Value to Select Different Lanes
2. Set the value of test_in[63:32] in the file altpcie_sv_hip_ast_hwtcl.v
In the file: altpcie_sv_hip_ast_hwtcl.v, change line 2929
From
.test_in ({testin[63:1],(ALTPCIE_SV_HIP_AST_HWTCL_SIM_ONLY==0)?1'b0:testin[0]}),
To
.test_in ({32’h<n>,testin[31:1],(ALTPCIE_SV_HIP_AST_HWTCL_SIM_ONLY==0)?1'b0:testin[0]}),
Note <n> = 0 to 3 based on the above table
3. Observe the PIPE interface signals from testout in the module altpcie_sv_hip_ast_hwtcl
You can observe the corresponding PIPE interface signals on the 320 bit test_out bus, also referred to as testout, in the module altpcie_sv_hip_ast_hwtcl. The following table shows the PIPE interface signals for particular lanes on the testout bus. You can observe the testout bus using SignalTap™ II, register map, or general purpose I/Os.
PIPE Interface Signals | Bit Width | Lane 0/Lane 2/Lane 4/Lane 6 | Lane 1/Lane 3/Lane 5/Lane 7 |
reserved - not used | 58 | testout[159:102] | testout[319:262] |
lanereversalenable | 1 | testout[101] | testout[261] |
eidleinfersel | 3 | testout[100:98] | testout[260:258] |
txdeemph | 1 | testout[97] | testout[257] |
txmargin | 3 | testout[96:94] | testout[256:254] |
rate | 2 | testout[93:92] | testout[253:252] |
rxstatus | 3 | testout[91:89] | testout[251:249] |
rxelecidle | 1 | testout[88] | testout[248] |
phystatus | 1 | testout[87] | testout[247] |
rxvalid | 1 | testout[86] | testout[246] |
rxblkst | 1 | testout[85] | testout[245] |
rxsynchd | 2 | testout[84:83] | testout[244:243] |
rxdataskip | 1 | testout[82] | testout[242] |
rxdatak | 4 | testout[81:78] | testout[241:238] |
rxdata | 32 | testout[77:46] | testout[237:206] |
powerdown | 2 | testout[45:44] | testout[205:204] |
rxpolarity | 1 | testout[43] | testout[203] |
txcompl | 1 | testout[42] | testout[202] |
txelecidle | 1 | testout[41] | testout[201] |
txdetectrx | 1 | testout[40] | testout[200] |
txblkst | 1 | testout[39] | testout[199] |
txsynchd | 2 | testout[38:37] | testout[198:197] |
txdataskip | 1 | testout[36] | testout[196] |
txdatak | 4 | testout[35:32] | testout[195:192] |
txdata | 32 | testout[31:0] | testout[191:160] |