How can I observe the Hard IP for PCI Express PIPE interface signals for Arria V GZ and Stratix V devices?

To use the Hard IP for PCI Express® test bus in conjunction with SignalTap™ II, a register map, or general purpose IOs to observe the PIPE interface signals on Arria® V GZ and Stratix® V devices. Follow the instructions below:

The test bus consists of test_in bus and test_out bus. The test bus is designed for debugging purposes only and should not be used in production designs.

The test_in bus determines which Hard IP PIPE interface signals to route to the test_out bus for observation.  The upper 32 bits of the test_in bus in the file altpcie_sv_hip_ast_hwtcl.v is used to select two of eight PCIe lanes. The PIPE signals for these two lanes are routed to the 320 bit test_out bus (also refered to as testout in the same file).

1. Determine the value for the upper 32 bits of the test_in bus

Only the upper 32 bits of the test_in bus are used to select the PIPE interface signals for two specific PCIe lanes at a time. Table 1 shows the test_in[63:32] value to select the lanes. 

Table 1. Test_in[63:32] Value to Select Different Lanes

2. Set the value of test_in[63:32] in the file altpcie_sv_hip_ast_hwtcl.v

In the file: altpcie_sv_hip_ast_hwtcl.v, change line 2929

From    

.test_in ({testin[63:1],(ALTPCIE_SV_HIP_AST_HWTCL_SIM_ONLY==0)?1'b0:testin[0]}),

To

.test_in ({32’h<n>,testin[31:1],(ALTPCIE_SV_HIP_AST_HWTCL_SIM_ONLY==0)?1'b0:testin[0]}),

Note <n> = 0 to 3 based on the above table

3. Observe the PIPE interface signals from testout in the module altpcie_sv_hip_ast_hwtcl

You can observe the corresponding PIPE interface signals on the 320 bit test_out bus, also referred to as testout, in the module altpcie_sv_hip_ast_hwtcl. The following table shows the PIPE interface signals for particular lanes on the testout bus. You can observe the testout bus using SignalTap™ II, register map, or general purpose I/Os.