Why does the Intel® L-/H-Tile Avalon® Streaming IP for PCI Express* report timing violations on clock domain crossing paths?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3 to 21.2, you may see timing violations between paths that are crossing clock domains in the Intel® L-/H-Tile Avalon® Streaming IP for PCI Express*.

The Intel® L-/H-Tile Avalon® Streaming IP for PCI Express* generates the required synchronization logic for the clock domain crossing, however, the Synopsys* Design Constraints Files (.sdc) does not correctly constrain these paths.

To work around this problem, follow the next steps:

1. Download altera_pcie_s10_gen3x16_cdc Synopsys* Design Constraints file (.sdc)
2. Add altera_pcie_s10_gen3x16_cdc.sdc to your Intel® Quartus® project
3. altera_pcie_s10_gen3x16_cdc.sdc should be placed after the Intel® L-/H-Tile Avalon® Streaming IP for PCI Express* configuration file (.ip)

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.