Article ID: 000075590 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Have the MLAB device timing models changed since the release of the Quartus II software version 8.1?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, since the release of the Quartus ® II software version 8.1, there is an update for the the MLAB device timing models that provides a robust timing model for the MLAB block.

    The following devices are affected by this timing model update:

    • EP3SL110
    • EP3SL150
    • EP3SL340
    • EP3SE80
    • EP3SE110

    Affected devices using MLABs can see an MLAB hold time violation, if the Beneficial Skew
    Optimization option is set to ON or if the MLAB uses any locally routed clocks. To verify these conditions, follow these steps:

    1. To determine if your design uses MLAB, look for MLAB in the <project name>.fit.rpt file or the Fitter RAM Summary of the Fitter Compilation Report in the GUI. The type is MLAB.
    2. To determine if Beneficial Skew Optimization is set to ON, look in the <project name>.qsf for the following setting:

      set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
    3. To check for any locally routed clocks, look in the <project name>.fit.rpt or the Controls Signals
      section of the Fitter Compilation Report in the GUI. Each locally routed clock has Global set to NO.

    The Quartus II software version 9.0 contains the updated MLAB timing models for the affected devices. For designs implementing MLABs under the above stated conditions, follow these steps:

    1. Install the Quartus II software version 9.0.
    2. Perform a full recompilation of the design.
    3. Verify no timing violations occur.
    4. If no timing violations occur, no further action is required. If a timing violation occurs, further optimize the design. When the design is fully optimized, reprogram any existing devices already in the field and all future devices with the newly generated programming file.

    For more information relating to the changes to the MLAB timing model, refer to the Stratix III Device Family Errata Sheet (PDF).

    Related Products

    This article applies to 1 products

    Stratix® FPGAs