Article ID: 000075589 Content Type: Troubleshooting Last Reviewed: 07/20/2021

Why does the P-Tile Debug Toolkit display lanes 8 – 15 registers in the P0 Configuration Space of a design configured in x8x8 mode ?

Environment

  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.2, lanes 8 – 15 registers are displayed in the P0 Configuration Space of a design configured in x8x8 mode. P0 Configuration Space should display lanes 0 – 7 registers only.

    Resolution

    In version 21.2 of the Intel® Quartus® Prime software, simply ignore the lane 8 – 15 registers shown in the P0 Configuration Space.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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