Article ID: 000075587 Content Type: Troubleshooting Last Reviewed: 08/09/2022

Why does the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example use the CML IO standard on the PCI Express reference clock input pins?

Environment

  • Intel® Quartus® Prime Pro Edition
  • example-design-components
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example, the default I/O standard for the PCI Express reference clock input pins is CML.

     

    Resolution

    According to the PCI Express Base Specification and the Intel® Agilex™ Device Family Pin Connection Guidelines, the reference clock input pins should be set to HCSL I/O standard.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. 

     

     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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