Description
Due to a problem in the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example, the default I/O standard for the PCI Express reference clock input pins is CML.
Resolution
According to the PCI Express Base Specification and the Intel® Agilex™ Device Family Pin Connection Guidelines, the reference clock input pins should be set to HCSL I/O standard.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
