Article ID: 000075584 Content Type: Troubleshooting Last Reviewed: 05/25/2021

The Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example is not functional in hardware.

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 DX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Intel® Stratix® 10  E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example available in the Intel® Quartus® Prime Pro versions 21.1 supports simulation using the provided testbench in both Synopsys* VCS* and Mentor* Modelsim.

    Hardware test is not supported in version 21.1 of the Intel® Quartus® Prime software.

    Timing analyzer may report timing violations when compiling the example design in version 21.1 of the Intel® Quartus® Prime software.

    Resolution

    To work around this problem in Intel® Quartus® Prime Pro software version 21.1 install the patch below:

    Download the version 21.1 patch 0.15 for Linux (.run)

    Download the version 21.1 patch 0.15 for Windows* (.exe)

    Download the Readme for version 21.1 patch 0.15 (.txt)

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro software.

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