Article ID: 000075567 Content Type: Troubleshooting Last Reviewed: 06/18/2018

Why doesn't the Intel® Arria® 10 PCI* Express HIP set pattern lock bit when received modified compliance pattern at LTSSM=Polling Compliance state ?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    According to PCIe* specification, when the LTSSM of PCIe* Root Port or Endpoint is in the polling compliance state, the pattern lock bit in transmitted data should be set, when it receives modified compliance pattern and locks to the modified compliance pattern. Intel® Arria® 10 PCIe* Hard IP has a problem which means it will never lock to the modified compliance pattern. Intel Arria 10 PCIe* Hard IP is expecting data pattern 4A_BC_B5_BC { D10.2, K28.5, D21.5, K28.5 } to be one of the following sequence:

    1.  BC_4A_B5_BC { K28.5, D10.2, D21.5, K28.5 }
    2.  BC_BC_4A_B5 { K28.5, K28.5, D10.2, D21.5 }
    3.  B5_BC_BC_4A { D21.5, K28.5, K28.5, D10.2 }
    4.  4A_B5_BC_BC { D10.2, D21.5, K28.5, K28.5 }

     

    Resolution

    No workaround for this Errata. The user application needs to be aware of the limitation and take care of this scenario.

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