Article ID: 000075565 Content Type: Troubleshooting Last Reviewed: 01/29/2018

Why does the Intel® Arria® 10 and Intel Cyclone® 10 PCI* Express Gen1 and Gen2 PIPE PHY fail to link train correctly?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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Critical Issue

Description

Due to a problem with the Intel® Quartus® Prime version 17.1 and earlier transceiver calibration code, Intel Arria® 10 and Intel Cyclone® 10 PCIe* PIPE PHYs configured for Gen1 and Gen2 configurations may fail to link train correctly and reach the L0 state.

Resolution

This problem has been fixed starting in Intel Quartus Prime v17.1.1. 

 

Related Products

This article applies to 4 products

Intel® Arria® 10 GX FPGA
Intel® Cyclone® 10 FPGAs
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 SX SoC FPGA

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