Article ID: 000075560 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why does the HDMI 2.1 Intel® FPGA Design Example occasionally fail to read the HDMI sink receiver EDID after a hotplug or reset event?

Environment

  • Intel® Quartus® Prime Pro Edition
  • HDMI Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem starting in version 19.4 of the Intel® Quartus® Prime Pro software when using the Intel® Arria® 10 Devices, and version 20.4 of the Intel® Quartus® Prime Pro software when using the Intel® Stratix® 10 devices, the HDMI Intel® FPGA Source IP core may fail to read the HDMI sink receiver EDID after a hotplug or reset event.

    This is due to the HDMI Intel® FPGA Source IP core FLT_update polling timer continuing to run when the HDMI Tx cable is unplugged. This problem causes corruption to I2C master software design and prevents it from being able to correctly read back the EDID content. 

    Resolution

    This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 21.1 software. 

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs