Article ID: 000075554 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the simulation behavior for rx_phase_comp_fifo_error when there is a difference between the read and write clock frequencies in Cyclone IV GX devices?

Environment

  • Cyclone® IV GX FPGA
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Description

In simulation, the rx_phase_comp_fifo_error signal for Cyclone® IV GX devices will assert when there is a difference in frequency between the read and write clocks of the phase compensation FIFO.  Once asserted, rx_phase_comp_fifo_error will remain asserted until rx_digital_reset is asserted.

However, if the read clock does not toggle in the simulation test bench, the rx_phase_comp_fifo_error signal will not assert.  This does not match actual device behavior where rx_phase_comp_fifo_error will assert if the read clock is not toggling.

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