Article ID: 000075551 Content Type: Troubleshooting Last Reviewed: 09/11/2018

When using the Intel® Stratix® 10, H-tile Hard IP for Ethernet Intel® FPGA IP, oversized frame stripping can cause invalid frames to be presented to user logic.

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When the H-tile Hard IP for Ethernet Intel® FPGA IP RX MAC receives frame size >= 65536, and enforce_max_frame_size is enabled, the frame output from RX MAC to user logic will be truncated to the frame size specified by max_rx_frame_size setting. A second invalid frame will output from RX MAC to user logic starting from byte-65536 to end of the super large frame.

    Resolution

    No workaround or fix is available for this errata problem.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

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