Article ID: 000075539 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is there a voltage drop in single-ended I/O standards when located on dedicated differential input pins on side I/O banks in Stratix III devices for designs compiled in Quartus II software version 8.0 and version 8.1?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Quartus® II software version 8.0 and version 8.1 incorrectly enable an internal resistor between two I/Os of a side bank dedicated differential input pair when each I/O is configured as single-ended and any of the following conditions are true:

  • The current strength is not specified
  • The input parallel on chip termination (OCT) option for the I/O is enabled
  • The output series OCT option for the I/O is enabled

This problem affects only Stratix® III and Stratix® IV devices. 

If both I/Os in this pair are input-only, the internal resistor is enabled incorrectly only if the input parallel termination option for either input is enabled. This resistor may cause the I/O pin to malfunction when it is single-ended by reducing the complementary pin voltage.

This problem is fixed in the Quartus II software version 8.0 SP1 and version 9.0 and above. Get the latest Quartus II software version from the Download Center.

To correct this problem in the Quartus II software version 8.0 and 8.1, if you cannot upgrade to the latest version, download and install patch 0.22 for version 8.0 and patch 0.50 for version 8.1 from the following locations:

 

Patch for Quartus II software version 8.0:

Quartus II 8.0 Patch 0.22 for PC

Quartus II 8.0 Patch 0.22 for PC readme.txt

Quartus II 8.0 Patch 0.22 for Linux

Quartus II 8.0 Patch 0.22 for Linux readme.txt

 

Patch for Quartus II software version 8.1:

Quartus II 8.1 Patch 0.50 for PC

Quartus II 8.1 Patch 0.50 for PC readme.txt

Quartus II 8.1 Patch 0.50 for Linux

Quartus II 8.1 Patch 0.50 for Linux readme.txt

 

Related Products

This article applies to 3 products

Stratix® III FPGAs
Stratix® IV FPGAs
Stratix® IV GX FPGA