Article ID: 000075536 Content Type: Troubleshooting Last Reviewed: 08/14/2018

Why does the Intel® Arria® 10 PCIe* Hard IP treat nullified TLPs (including posted TLPs and non-posted TLPs) as correctable error and set the correctable error register?


  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Cyclone® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express

    Critical Issue


    According to the PCIe* spec, when a PCIe* physical layer receives nullified TLPs (including posted and non-posted TLPs), it should discard the nullified TLPs and free any storage allocated for these TLPs. Due to a problem with the Intel® Arria® 10 PCIe* Hard IP, when it receives nullified TLPs, it treats them as correctable error and sets the correctable error register.


    No workaround for this problem exists. The user application should be aware of the limitation and take care of this scenarios. If correctable errors are reported by the Intel® Arria® 10 PCIe* Hard IP, the user application can ignore these if they are caused by nullified packets. Typically nullified packets are only utilized in PCIe* Switch applications.

    This problem will not be fixed in a future release of the Intel® Quartus® Prime software.



    All postings and use of the content on this site are subject to Terms of Use.