Article ID: 000075535 Content Type: Troubleshooting Last Reviewed: 03/10/2023

Why is waitrequest still high after readdatavalid is asserted in ASMI Parallel II Intel® FPGA IP?

Environment

    Intel® Quartus® Prime Pro Edition
    ASMI Parallel II Intel® FPGA IP
    Avalon-MM Pipeline Bridge Intel® FPGA IP
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Description

Due to a problem with the ASMI Parallel II Intel® FPGA IP, you will see this behavior if the read signal is asserted when the IP is stalling a new command with waitrequest high. The readdatavalid signal will be asserted one clock cycle after the read signal is asserted.  

Because the IP is still busy, waitrequest stays high. The readdata bus from the IP is not valid.

 

 

Resolution

To work around this problem, do not send the read command to the IP when the waitrequest is high.

Send the read command when waitrequest signal is deasserted.

 

Related Products

This article applies to 5 products

Intel® FPGA Configuration Device EPCQ-A
Intel® FPGA Configuration Devices
Intel® FPGA Configuration Device EPCQ
Intel® Programmable Devices
Intel® FPGA Configuration Device EPCQ-L

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