Article ID: 000075532 Content Type: Troubleshooting Last Reviewed: 02/26/2018

Why does the Intel® Low Latency 40-GbE IP core fail Auto-Negotiation when the master lane is selected as 0, 1, or 3?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 40G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • Low Latency 40G 100G Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Arria® 10 Low Latency 40GBASE-KR4 logic implementation, Auto-Negotiation(AN) may fail prior to Intel Quartus® Prime softwar version 16.0 update1.

    The IP core might fail AN if the master lane is selected as 0, 1, or 3, due to timing issues internal to the core.

    As this problem is caused by a timing issue, simulation will work correctly.

    Resolution

    To work around this problem, set the master lane as 2.

    This problem has been fixed in the Intel Quartus Prime software version 16.0 update 1.

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