Error: Can't place Top/Bottom or Left/Right PLL <signal name> (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device

You will get this error message if you have assigned a non-dedicated clock pin to the input port of a PLL.  Refer to the respective device handbook for information on which clock pins are dedicated to respective PLLs in the device you are targeting.

To resolve this error message, you can manually change the pin assignment to a dedicated clock pin for the respective PLL using the Pin Planner or Assignment Editor.  Alternatively, you can delete the assignment in your <project name>.qsf file and let the Quartus® II design software select the best possible dedicated clock pin.