Description
In the Stratix® IV Hard IP for PCI Express®, some configurations allowed the pld_clk to be driven from a PLL that was, in turn, derived from coreclkout_hip. This implementation is not supported when using the Stratix V Hard IP.
Resolution
For Stratix V, connect pld_clk to coreclkout_hip as shown in the Clock Signals Hard IP Implementation table of the Clock Signals section of the Stratix V Hard IP for PCI Express User Guide.