Article ID: 000075509 Content Type: Troubleshooting Last Reviewed: 01/11/2015

Why do I see incorrect transceiver dynamic reconfiguration behavior when using Quartus II software version 14.1 of the Native PHY IP core for Arria 10 devices?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in Quartus® II software version 14.1 you may see incorrect transceiver dynamic reconfiguration behavior of channels other than channel 0 of an Arria® 10 device, multi-channel Native PHY IP core when the Share reconfiguration interface option is disabled.

    When the Share reconfiguration interface option is disabled, the reconfig_writedata port of channel 0 is erroneously applied to all channels of the Native PHY IP core.

    Resolution

    To work around this problem you can enable the Share reconfiguration interface option in the Native PHY IP core.

    This problem will be fixed in a future version of the Quartus II software.

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