Article ID: 000075501 Content Type: Troubleshooting Last Reviewed: 02/09/2018

Why does the Viterbi IP core output incorrect data when sink_val signal is not constantly driven high?

Environment

    Intel® Quartus® Prime Pro Edition
    Viterbi Intel® FPGA IP
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Description

Due to a problem with the Intel® Quartus® Prime software version 16.0 and 16.1, you may encounter the above problem if the sink_val signal of the Viterbi IP core is not constantly driven high.

Resolution

This problem has been fixed in the Intel Quartus Prime software version 17.0.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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