Due to a problem in the Intel® Quartus® Prime Pro Edition software versions 21.1 and 21.2, the above error message will be observed during the fitter stage, when using the HCSL IO standard for the reference clock input pins for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*.
To work around this problem in the Intel® Quartus® Prime Pro Edition software versions 21.1 and 21.2, set the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* reference clock input as the CML IO standard. The reference clock driving these clock pins must be HCSL, as per the PCI Express Base Specification and the Intel® Agilex™ Device Family Pin Connection Guidelines.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.
