Article ID: 000075495 Content Type: Error Messages Last Reviewed: 07/19/2021

Error (12341): The input pin has a HCSL I/O standard, but the selected device does not support input pin operation with a HCSL I/O standard.

Environment

  • Intel® Quartus® Prime Pro Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software versions 21.1 and 21.2, the above error message will be observed during the fitter stage, when using the HCSL IO standard for the reference clock input pins for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition software versions 21.1 and 21.2, set the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* reference clock input as the CML IO standard. The reference clock driving these clock pins must be HCSL, as per the PCI Express Base Specification and the Intel® Agilex™ Device Family Pin Connection Guidelines.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software. 

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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