Why does my design, including an R-Tile Avalon Streaming IP for PCI Express*, fail to successfully undergo reconfiguration or a CVP Update operation?

You may experience an error while reconfiguring or performing a CVP update on your device if there is no stable free running clock signal on the reference clock pins (REFCLK_GXR[R,L [14A,14C,15A,15C]_CH[0,1]P) of the R-Tile before going through the reconfiguration process.

The problem will not affect your device during the first configuration process even if there is no stable free running clock signal on the reference clock pins (REFCLK_GXR[R,L [14A,14C,15A,15C]_CH[0,1]P).

Provide a stable free running clock signal on the reference clock pins (REFCLK_GXR[R,L [14A,14C,15A,15C]_CH[0,1]P) of the R-Tile before starting a device reconfiguration operation.

This information has been added in the Agilex™ FPGA Configuration User Guide.