Are there any known problems with the register settings contained in the ‘c3_reconfig.c’ file generated by the E-tile Hard IP Dynamic Reconfiguration Design Example for Intel® Stratix® 10 FPGA?

Are there any known problems with the register settings contained in the ‘c3_reconfig.c’ file generated by the E-tile Hard IP Dynamic Reconfiguration Design Example for Intel® Stratix® 10 FPGA operating in the “25G Ethernet to CPRI Protocol” , "10G/25G Ethernet Protocol" or the “CPRI Protocol” modes?

Yes. Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 20.3 and earlier, the ‘c3_reconfig.c’ file generated by the E-tile Hard IP Dynamic Reconfiguration Design Example  Intel® Stratix® 10 FPGA operating in the “25G Ethernet to CPRI Protocol”, "10G/25G Ethernet Protocol"  or “CPRI Protocol” modes contains incorrect register writes to transceiver register address 0x30E, bit [7]. These writes can be found in the following functions:

                        “25G Ethernet to CPRI Protocol”

                                •       c3_ehiplane_rcfg_25gptpfec_to_9p8gcpri

                                •       c3_ehiplane_rcfg_25gptpfec_to_4p9gcpri

                                •       c3_ehiplane_rcfg_25gptpfec_to_2p4gcpri

                                •       c3_ehiplane_rcfg_10gcpri_to_9p8gcpri

                        “10G/25G Ethernet Protocol”

                                •       c3_ehiplane_rcfg_25gptpfec_to_1gptp

                                •       c3_ehiplane_rcfg_10gptp_to_1gptp

                                •       c3_ehiplane_rcfg_25gptpnofec_to_1gptp

                        “CPRI Protocol”

                                •       c3_cpriphy_rcfg_grp_a_to_grp_b

                                •       c3_cpriphy_rcfg_grp_a_to_grp_c

Within each of these functions, the following register accesses are incorrect:

    // HIP OSC CLK SCG EN

    rdata0 = IORD(xcvr_base_addr, 0x30E);

    wdata = (rdata0 & 0xFFFFFF7F) | 0x80;

    IOWR(xcvr_base_addr, 0x30E, wdata);

To work around this problem, perform the following steps:

1. Navigate to the “/software/dynamic_reconfiguration_hardware/” directory.
2. Open the ‘c3_reconfig.c’ file.
3. Locate the functions cited in the description above.
4. Comment out the following (3) sections of the code:

                // HIP OSC CLK SCG EN

                rdata0 = IORD(xcvr_base_addr, 0x30E);

                wdata = (rdata0 & 0xFFFFFF7F) | 0x80;

                IOWR(xcvr_base_addr, 0x30E, wdata);

5. Save the ‘c3_reconfig.c’ file.
6. Re-build the Nios software project to obtain a new .elf file.