Article ID: 000075490 Content Type: Troubleshooting Last Reviewed: 01/13/2021

Are there any known problems with the register settings contained in the ‘c3_reconfig.c’ file generated by the E-tile Hard IP Intel® Stratix® 10 Dynamic Reconfiguration Design Example

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Quartus® Prime Pro Edition
  • CPRI
  • Ethernet
  • Reference Design Components
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Are there any known problems with the register settings contained in the ‘c3_reconfig.c’ file generated by the E-tile Hard IP Intel® Stratix® 10 Dynamic Reconfiguration Design Example operating in the “25G Ethernet to CPRI Protocol” , "10G/25G Ethernet Protocol" or the “CPRI Protocol” modes?

    Yes. Due to a problem in the Intel® Quartus® Prime Pro software versions 20.3 and earlier, the ‘c3_reconfig.c’ file generated by the E-tile Hard IP Intel® Stratix® 10 Dynamic Reconfiguration Design Example operating in the “25G Ethernet to CPRI Protocol”, "10G/25G Ethernet Protocol"  or “CPRI Protocol” modes contains incorrect register writes to transceiver register address 0x30E, bit [7]. These writes can be found in the following functions:

                            “25G Ethernet to CPRI Protocol”

                                    •       c3_ehiplane_rcfg_25gptpfec_to_9p8gcpri

                                    •       c3_ehiplane_rcfg_25gptpfec_to_4p9gcpri

                                    •       c3_ehiplane_rcfg_25gptpfec_to_2p4gcpri

                                    •       c3_ehiplane_rcfg_10gcpri_to_9p8gcpri

                            “10G/25G Ethernet Protocol”

                                    •       c3_ehiplane_rcfg_25gptpfec_to_1gptp

                                    •       c3_ehiplane_rcfg_10gptp_to_1gptp

                                    •       c3_ehiplane_rcfg_25gptpnofec_to_1gptp

                            “CPRI Protocol”

                                    •       c3_cpriphy_rcfg_grp_a_to_grp_b

                                    •       c3_cpriphy_rcfg_grp_a_to_grp_c

     

    Within each of these functions, the following register accesses are incorrect:

        // HIP OSC CLK SCG EN

        rdata0 = IORD(xcvr_base_addr, 0x30E);

        wdata = (rdata0 & 0xFFFFFF7F) | 0x80;

        IOWR(xcvr_base_addr, 0x30E, wdata);

    Resolution

    To work around this problem, perform the following steps:

    1.)   Navigate to the “/software/dynamic_reconfiguration_hardware/” directory

    2.)   Open the ‘c3_reconfig.c’ file

    3.)   Locate the functions cited in the description above

    4.)   Comment out the (3) sections of code found below:

                    // HIP OSC CLK SCG EN

                    rdata0 = IORD(xcvr_base_addr, 0x30E);

                    wdata = (rdata0 & 0xFFFFFF7F) | 0x80;

                    IOWR(xcvr_base_addr, 0x30E, wdata);

     

    5.)   Save the ‘c3_reconfig.c’ file

    6.)   Re-buiild the NIOS software project in order to obtain a new .elf file

     

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro software.

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