Why is the out_channel of my multi input Intel® CIC IP core out of sequence?

Due to an error in the Intel® CIC IP core calculation of latency in the output block, the out_channel to out_data relationship is off by one. For example, if your CIC filter has 10 inputs, then out_data provides data for channel 0 while out_channel will indicate channel 9.  This channel alignment error will be present in both simulation and the synthesized design.

To work around this problem add one additional register stage after out_data. This stage can be added in RTL. This additional register stage corrects the out_channel to out_data relationship. 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.