Article ID: 000075464 Content Type: Troubleshooting Last Reviewed: 01/30/2018

Why does synthesis of Intel® Arria® 10 PCIe* IP generated with VHDL return Error(16045) - ""u_global_buffer_coreclkout" instantiates undefined entity "altera_global""?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Quartus® Prime software version 17.1, the altera_global component entity alias in VDHL is not mapped to the correct VHDL altera_global entity. 

    Resolution

    In the PCIe* top-level VHDL instantiation file, for example pcie_pcie_a10_hip_0.vhd, comment out these two lines of VHDL code.  Then re-run the implementation. 

      for pcie_a10_hip_0 : pcie_pcie_a10_hip_0_altera_pcie_a10_hip_171_<random string>_cmp

            use entity altera_pcie_a10_hip_171.pcie_pcie_a10_hip_0_altera_pcie_a10_hip_171_<same random string>; 

    This problem is scheduled to be fixed in a future Intel® Quartus® Prime software release.

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